The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In computer systems using a Peripheral Component Interconnect (PCI) bus, a plurality of device controllers may be installed in PCI bus slots to control devices such as disk drives, for example. Each controller may issue an interrupt to a host processor when the controller generates a service request. For example, a controller may issue an interrupt when the controller needs to perform an input/output (I/O) operation, where data needs to be transferred, for example, from a device such as a disk drive to system memory or vice versa.
Typically, the PCI bus uses four interrupts. While each controller can be set to issue a different interrupt, most controllers are typically set to issue the same interrupt. When a controller issues an interrupt, the controller typically pulls a signal on the bus to a predetermined state (e.g., low or high). On receiving the interrupt, a basic input output system (BIOS) of the computer system polls the controllers to determine which controller issued the interrupt. Polling increases overhead of the PCI bus.
PCI Express (PCIe) bus may use Message Signaled Interrupts (MSI's). A controller using MSI's issues an interrupt by writing a system-specified data value to a system-specified memory location in main memory of the computer system. During system initialization (i.e., startup or boot process), the host programs each controller with an address of a memory location in the main memory and the data value to write in the memory location when issuing an interrupt.
For example, the host may populate a data structure in the controller with the addresses of a memory location and a corresponding data value. The address and data value corresponds to an interrupt that can be generated by a portion of hardware in the controller. Additional MSI interrupts can be generated using the address populated in the data structure by incrementing by one the data value programmed in the data structure.
MSIs allow a controller to issue up to 32 interrupts, each interrupt corresponding to a unique value in the lower 5 bits of the data value programmed into the data structure. For example, one interrupt can be generated by a write portion of the controller for writing data to the main memory while another interrupt can be generated by a read portion of the controller for reading data from the main memory.
PCIe bus may also use MSI-X interrupts. A controller using MSI-X issues an interrupt by writing a system-specified data value to a system-specified memory location in main memory of the computer system. During system initialization (i.e., startup or boot process), the host programs each controller with an address of a memory location in the main memory and the data value to write to the memory location when issuing an interrupt.
For example, the host may populate a table in the controller with the addresses of a memory location and a corresponding data value. The address and data value corresponds to an interrupt that can be generated by a portion of hardware in the controller. The host may enable additional MSI-X interrupts by populating address and data values into other entries in the table in the controller.
Each interrupt is assigned a separate address and data value. When a controller issues an interrupt, the host determines which controller issued the interrupt based on the address of the memory location written to and the data value written to the memory location. Extended MSI's (MSI-X) allow a controller to issue a larger number of interrupts (up to 2048).
In controllers using MSI or MSI-X interrupts, after an interrupt for a service request has been sent to the host, another interrupt for the same service request may be sent to the host at any time. In a system that performs one million I/O Operations per Second (IOPs), this can result in an interrupt being sent once every microsecond on average. A controller typically includes a Pending Bit Array (PBA), where a bit is set when an interrupt is scheduled to be sent to an interrupt controller. The bit is reset when the interrupt is sent to the interrupt controller. Multiple bits may be set at the same time when there are multiple interrupts scheduled to be sent to the interrupt controller.